High speed synchronous circuits in which a controller drives multiple loads are known. Typical examples include synchronous dynamic random access memory (SDRAM) circuits with multiple memory ranks. In synchronous circuits, a controller typically provides a common clock used to provide a common timing reference.
As clock rates used in these circuits are very high, signals on some signal lines drive multiple modules may not settle to be reliably sampled within one clock cycle. Thus, designs that take this into account usually allow slow settling signals connected to multiple modules to settle in two or three clock cycles. Such timing arrangements, in which signals are not sampled within the same clock cycle in which they are produced, but in the subsequent second or third clock cycle, are sometimes called 2T or 3T timing respectively. Signals that are required to settle in a single clock cycle may be said to meet 1T timing.
Signals that drive multiple loads may often need to settle before the next rising or falling edge of a clock that is used by a receiving device or subsystem for sampling the signal. That is, they must meet 1T timing. This can be observed for instance, in SDRAM which are double data rate (DDR). DDR memory modules have become very common as they offer higher bandwidth than their single data rate (SDR) counterparts, by reading and/or writing data during both the rising and falling edges of the clock. In DDR SDRAM interface circuits, some control signals such as clock-enable and chip-select signals must always be in 1T timing mode. Data in DDR SDRAM circuits is transferred at double the clock rate. Data lines are sampled with a strobe at both rising and falling edges so data signals must settle within half clock (strobe) period.
Such design constraints in high speed interface circuits, in which signal lines interconnect many modules, are often difficult to meet. The time it takes for the signal level on a line to transition to logic high or logic low level depends in part on the electrical load connected to the line. Stringent timing constraints are particularly difficult to meet on a signal line that is interconnected to multiple modules, as the trace characteristic impedance connecting the multiple modules, and the capacitive load of the multiple modules may not permit fast settling of the signal to a desired signal level. If timing requirements are not met, signals may be ambiguously or inaccurately decoded.
Consequently, to ensure timing requirements are met, high speed interface circuits driving multiple loads typically use separate signal lines to each of the modules, for signals that should meet 1T timing. With separate signal lines, the load on each line is reduced to just one module (load), and thus stricter timing requirements can be met.
Unfortunately, providing multiple drivers and routing multiple individual lines connected to individual modules, rather than sharing the same signal line is often complex and expensive. When such circuits are part of an integrated circuit (IC), the size of the die on which the IC may be formed is increased, as a result of the increased signal lines interconnecting the various modules to the controller.
In cases where the controller is a discrete component separate from the loads, its input-output ring or pin count would increase as more connections are needed. All these factors increase the cost of manufacturing the circuit.
Clearly, an improved controller for use in synchronous circuits and methods to provide shared signals is desirable.